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general description the max5556 stereo audio sigma-delta digital-to-analog converter (dac) offers a simple and complete stereo dig - ital-to-analog solution for media servers, set-top boxes, video-game hardware, and other general consumer audio applications. this dac features built-in digital interpo - lation/filtering, sigma-delta digital-to-analog conversion, and analog output filtering. control logic and mute cir - cuitry minimize audible pops and clicks during power-up, power-down, clock changes, or when invalid clock condi - tions occur. the max5556 receives input data over a 3-wire i 2 s-compatible interface with left-justified audio data. data can be clocked by either an external or internal serial clock. the internal serial clock frequency is pro- grammable by selection of a master clock (mclk) and sample clock (lrclk) ratio. sampling rates from 2khz to 50khz are supported. the max5556 operates from a single +4.75v to +5.5v analog supply with total harmonic distortion plus noise below -87db. this device is available in an 8-pin so pack - age and is specified over the -40c to +85c industrial temperature range. applications digital video recorders and media servers set-top boxes video-game hardware features simple and complete stereo audio dac solutions, no controls to set sigma-delta stereo dacs with built-in interpolation and analog output filters i 2 s-compatible digital audio interface clickless/popless operation 3.5v p-p output voltage swing -87db thd+n +87db dynamic range sample frequencies (f s ) from 2khz to 50khz master clock (mclk) up to 25mhz automatic detection of clock ratio (mclk/ lrclk) +denotes a lead(pb)-free/rohs-compliant package. for leaded version, contact factory. *contact factory for availability. part temp range pin- package data format max5556esa+ -40c to +85c 8 so left-justified i 2 s data gnd outr mclk 1 + 2 8 7 outl v dd sclk lrclk sdata so top view 3 4 6 5 max5556 mclk lrclk sclk sdata gnd v dd outr outl clock filter filter dac dac +5v left output right output line-level buffer line-level buffer audio decompression max5556 serial interface max5556 low-cost stereo audio dac 19-0550; rev 3; 4/15 pin coniguration ordering information typical operating circuit evaluation kit available downloaded from: http:///
v dd to gnd ......................................................... -0.3v to +6.0v outl, outr, sdata to gnd ................ -0.3v to (v dd + 0.3v) current any pin (excluding v dd and gnd) ..................... 10ma outl, outr shorted to gnd .............................. continuous sclk, lrclk, mclk to gnd ............................. -0.3v to +6.0v continuous power dissipation (t a = +70c) 8-pin so (derate 5.88mw/c above +70c) ............... 471mw package thermal resistance ( ja ) .............................. 170c/w operating temperature range ........................... -40c to +85c junction temperature ...................................................... +150c storage temperature range ............................ -65c to +150c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c (v dd = +4.75v to +5.5v, v gnd = 0v, r out _ = 10k ? , c out _ = 10pf, 0dbfs sine-wave signal at 997hz, f lrclk (f s ) = 48khz, f mclk = 12.288mhz, measurement bandwidth 10hz to 20khz, t a = -40c to +85c, outputs are unloaded, unless otherwise noted. typical values at v dd = +5v, t a = +25c.) (note 1) parameter symbol conditions min typ max units power supply supply voltage v dd 4.75 5.0 5.50 v supply current i dd up to 48ksps 13 15 ma static digital 6 8.5 power dissipation up to 48ksps 65 82.5 mw static digital 30 44 dynamic performance (note 2)dynamic range, 16-bit unweighted 84 86 db a-weighted 86 90 dynamic range, 18-bit to 24-bit unweighted 87 db a-weighted 91 total harmonic distortion plusnoise, 16-bit thd+n 0dbfs -86 -81 db -20dbfs -67 -60dbfs -26 -24 total harmonic distortion plusnoise, 18-bit to 24-bit thd+n 0dbfs -87 db -20dbfs -68 -60dbfs -27 interchannel isolation 1khz full-scale output (crosstalk) 94 db combined digital and integrated analog filter frequency response (note 3) passband -0.5db corner 0.46 f s -3db corner 0.49 -6db corner 0.50 frequency response/passbandripple 10hz to 20khz (f s = 48khz) -0.025 +0.08 db 10hz to 20khz (f s = 44.1khz) -0.025 +0.08 10hz to 16khz (f s = 32khz) -6.000 +0.073 stopband 0.5465 f s stopband attenuation 52 db group delay t gd 20/f s s passband group-delay variation ?t gd 20hz to 20khz 0.4/f s s www.maximintegrated.com maxim integrated 2 max5556 low-cost stereo audio dac electrical characteristics stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings downloaded from: http:///
(v dd = +4.75v to +5.5v, v gnd = 0v, r out _ = 10k ? , c out _ = 10pf, 0dbfs sine-wave signal at 997hz, f lrclk (f s ) = 48khz, f mclk = 12.288mhz, measurement bandwidth 10hz to 20khz, t a = -40c to +85c, outputs are unloaded, unless otherwise noted. typical values at v dd = +5v, t a = +25c.) (note 1) parameter symbol conditions min typ max units dc characteristicsinterchannel gain mismatch 0.1 0.4 db gain error -5 +5 % gain drift 100 ppm/c analog outputsfull-scale output voltage v outr , v outl v outl 3.25 3.5 3.75 v p-p dc quiescent output voltage v q input code = 0 2.4 v minimum load resistance r l 3 k ? maximum load capacitance c l 100 pf power-supply rejection ratio psrr v ripple = 100mv p-p , frequency = 1khz (note 4) 66 db pop and click suppressionmute attenuation 100 db power-up until bias established figure 11 360 ms valid clock to normal operation soft-start ramp time, figure 12 (note 5) 20 ms digital audio interface (sclk, sdata, mclk, lrclk) input-voltage high v ih 2.0 v input-voltage low v il 0.8 v input leakage current i in -10 +10 a input capacitance 8 pf timing characteristics input sample rate f s 2 50 khz mclk pulse-width low t mclkl mclk/lrclk = 512 10 ns mclk/lrclk = 384 20 mclk/lrclk = 256 20 mclk pulse-width high t mclkh mclk/lrclk = 512 10 ns mclk/lrclk = 384 20 mclk/lrclk = 256 20 external sclk modelrclk duty cycle (note 6) 25 75 % sclk pulse-width low t sclkl 20 ns sclk pulse-width high t sclkh 20 ns sclk period t sclk 1/(128 x f s ) ns lrclk edge to sclk risingsetup time t slrs 20 ns lrclk edge to sclk risinghold time t slrh 20 ns sdata valid to sclk risingsetup time t sds 20 ns sclk rising to sdata hold time t sdh 20 ns www.maximintegrated.com maxim integrated 3 max5556 low-cost stereo audio dac electrical characteristics (continued) downloaded from: http:///
note 1: 100% production tested at t a = +85c. limits to -40c are guaranteed by design. note 2: 0.5 lsb of triangular pdf dither added to data. note 3: guaranteed by design, not production tested. note 4: psrr test block diagram shown in figure 1 denotes the test setup used to measure psrr. note 5: volume ramping interval starts from establishment of a valid mclk to lrclk ratio. total time is proportional to the sample rate (f s ). 20ms based on 48ksps operation. note 6: in external sclk mode, lrclk duty cycles are not limited, provided all data formatting requirements are met. see figure 4. note 7: the lrclk duty cycle must be 50% 1/2 mclk period in internal sclk mode. note 8: the sclk/lrclk ratio can be set to 32, 48, or 64, depending on the mclk/lrclk ratio selected. see figure 4. (v dd = +4.75v to +5.5v, v gnd = 0v, r out _ = 10k ? , c out _ = 10pf, 0dbfs sine-wave signal at 997hz, f lrclk (f s ) = 48khz, f mclk = 12.288mhz, measurement bandwidth 10hz to 20khz, t a = -40c to +85c, outputs are unloaded, unless otherwise noted. typical values at v dd = +5v, t a = +25c.) (note 1) figure 1. psrr test block diagram parameter symbol conditions min typ max units internal sclk mode lrclk duty cycle (note 7) 50 % internal sclk period t isclk (note 8) 1/f sclk ns lrclk edge to internal sclkrising delay time t isclkr t isclk /2 ns sdata valid to internal sclkrising setup time t isds mclk period = t mclk t mclk + 10 ns t isdh t mclk mclk sdata lrclk sclk active clocks gnd v dd spectrum analyzer lout, rout z g audio signal generator (100mv p-p at 1khz) dc power supply (5vdc) max5556 + - www.maximintegrated.com maxim integrated 4 max5556 low-cost stereo audio dac electrical characteristics (continued) downloaded from: http:///
(v dd = +5v, v gnd = 0v, r out_ = 10k ? , c out_ = 10pf, t a = +25c, unless otherwise noted.) -110 -100 -80-90 -70 -60 -60 -40 -50 -30 -20 -10 0 thd+n vs. amplitude max5556 toc09 amplitude (dbfs) thd+n (dbr) unweighted a-weighted input = 1khz 18-bit signal integration bandwidth = 20hz to 20khz -100-110 0 -10-20 -30 -40 -50 -60 -70 -80 -90 -130 -120-140 0 2 4 6 8 10 12 14 16 18 20 frequency (khz) amplitude (dbr) twin-tone imd fft max5556 toc08 16,000-sample fft with 13khz and 14khz input signals -100-110 0 -10-20 -30 -40 -50 -60 -70 -80 -90 -130 -120-140 0 2 4 6 8 10 12 14 16 18 20 frequency (khz) amplitude (dbr) idle-channel noise fft max5556 toc07 16,000-sample fft with no input -100-110 0 -10-20 -30 -40 -50 -60 -70 -80 -90 -130 -120-140 0 2 4 6 8 10 12 14 16 18 20 frequency (khz) amplitude (dbr) -60dbfs fft max5556 toc06 16,000-sample fft using 1khz input -100-110 0 -10-20 -30 -40 -50 -60 -70 -80 -90 -130 -120-140 0 2 4 6 8 10 12 14 16 18 20 frequency (khz) amplitude (dbr) 0dbfs fft max5556 toc05 16,000-sample fft using 1khz input -0.25 -0.15-0.20 -0.05-0.10 0.05 0 0.10 0.200.15 0.25 0 0.1 0.2 0.3 0.4 0.5 passband ripple max5556 toc04 frequency (normalized to f s ) amplitude (db) -10 -7-8 -9 -6 -5 -4 -3 -2 -1 0 0.40 0.44 0.42 0.46 0.48 0.50 0.52 transition band detail max5556 toc03 frequency (normalized to f s ) amplitude (db) -100 -80-90 -60-70 -40-50 -30 -10-20 0 0.40 0.44 0.48 0.52 0.56 0.60 transition band max5556 toc02 frequency (normalized to f s ) amplitude (db) -100 -80-90 -60-70 -40-50 -30 -10-20 0 0 0.2 0.3 0.4 0.1 0.5 0.6 0.7 0.9 0.8 1.0 stopband rejection max5556 toc01 frequency (normalized to f s ) amplitude (db) maxim integrated 5 www.maximintegrated.com max5556 low-cost stereo audio dac typical operating characteristics downloaded from: http:///
(v dd = +5v, v gnd = 0v, r out_ = 10k ? , c out_ = 10pf, t a = +25c, unless otherwise noted.) 100ms/div power-up response v out 1v/div 0v max5556 toc15 5ms/div clock-loss mute recovery v out 1v/div 2.4v max5556 toc14 clockrestored lossof clock 5 76 10 98 11 12 1413 15 0 1.0 1.5 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 supply current vs. digital input voltage (v dig ) max5556 toc13 digital input voltage (v dig ) (v) supply current (ma) v ih v dig < v ih mute engaged v dd = +5.5v dc output v dig < v ih normal operation 5 87 6 9 10 11 12 13 14 15 4.75 5.05 4.90 5.20 5.35 5.50 supply current vs. supply voltage max5556 toc12 supply voltage (v) supply current (ma) input = 1khz, 0dbfs signalnormal operation static digital inputmute operation 0 2010 4030 6050 70 0 20 10 30 40 50 power dissipation vs. sample frequency max5556 toc11 sample frequency (khz) power dissipation (mw) v dd = +5v input = 1khz, 0dbfs signal -110 -100 -90 -80 -70 -60 0 8 10 4 6 2 12 14 16 18 20 unweighted thd+n vs. frequency max5556 toc10 frequency (khz) thd+n (dbr) input = 1khz 18-bit signal,integration bandwidth = 20hz to 20khz maxim integrated 6 www.maximintegrated.com max5556 low-cost stereo audio dac typical operating characteristics downloaded from: http:///
detailed description the max5556 stereo audio sigma-delta dac offers a complete stereo digital-to-analog system for consumer audio applications. the max5556 features built-in digital interpolation/filtering, sigma-delta digital-to-analog con - version and analog output filters (figure 2). control logic and mute circuitry minimize audible pops and clicks dur- ing power-up, power-down, and whenever invalid clock conditions occur. this stereo audio dac receives input data over a 3-wire i 2 s-compatible interface. the max5556 accepts left- justified i 2 s data of 16 or 24 bits. this dac also sup - ports a wide range of sample rates from 2khz to 50khz. direct analog output data is routed to the right or left output by driving lrclk high or low. see the clock and data interface section. the max5556 supports mclk/lrclk ratios of 256, 384, or 512. this device allows a change to the clock speed ratio without causing glitches on the analog out - puts by internally muting the audio during invalid clock conditions. the internal mute function ramps down the audio amplitude and forces the analog outputs to a 2.4v quiescent voltage immediately upon clock loss or change of ratio. a soft-start routine is then engaged when a valid clock ratio is re-established, producing clickless and popless continuous operation. the max5556 operates from a +4.75v to +5.5v analog supply and features +87db dynamic range with total har - monic distortion typically below -87db.interpolator the digital interpolation filter eliminates images of the baseband audio signal that exist at multiples of the input sample rate (f s ). the resulting upsampled frequency spectrum has images of the input signal at multiples of 8 x f s . an additional upsampling sinc filter further reduces upsampling images up to 64 x f s . these images are ulti - mately removed through the internal analog lowpass filter and the external analog output filter. sigma-delta modulator/dac the max5556 uses a multibit sigma-delta dac with an oversampling ratio (osr) of 64 to achieve a wide dynamic range. the sigma-delta modulator accepts a 3-bit data stream from the interpolation filter at a rate of 64 x f s (f s = lrclk frequency) and provides an analog voltage repre - sentation of that data stream. pin name function 1 sdata serial audio data input. data is clocked into the max5556 on the rising edge of the internal or external sclk. data is input in twos complement format, msb irst. the state of lrclk determines whether data is directed to outl or outr. 2 sclk external serial-clock input. data is strobed on the rising edge of sclk. 3 lrclk left-/right-channel select clock. drive lrclk low to direct data to outl or lrclk high to direct data to outr. 4 mclk master clock input. the mclk/lrclk ratio must equal to 256, 384, or 512. 5 outr right-channel analog output 6 gnd ground 7 v dd power-supply input. bypass v dd to gnd with a 0.1f capacitor in parallel with a 4.7f capacitor as close to v dd as possible. place the 0.1f capacitor closest to v dd . 8 outl left-channel analog output www.maximintegrated.com maxim integrated 7 max5556 low-cost stereo audio dac pin description downloaded from: http:///
integrated analog lowpass filter the dac output of the sigma-delta modulator is followed by an analog smoothing filter that attenuates high-frequency quantization noise. the corner frequency of the filter is approximately 2 x f s . integrated analog output buffer following the analog lowpass filter, the analog signal is routed through internal buffers to outr and outl. the buffer can directly drive load resistances larger than 3k ? and load capacitances up to 100pf (figure 3). figure 3. load-impedance operating region figure 2. functional diagram load resistance r l (k) 3 5 10 15 20 125100 7550 25 safe operating region 25 load capacitance c l (pf) interpolator sigma-delta modulator sigma-delta modulator analog lowpass filter analog lowpass filter sdata mclk lrclk sclk outloutr v dd gnd dacdac buffer internal reference interpolator buffer max5556 serial interface www.maximintegrated.com maxim integrated 8 max5556 low-cost stereo audio dac downloaded from: http:///
clock and data interface the max5556 strobes serial data (sdata) in on the ris - ing edge of sclk. lrclk routes data to the left or right outputs and, along with sclk, defines the number of bits per sample transferred. the digital interpolators filter data at internal clock rates derived from the mclk frequency. each device supports both internal and external serial clock (sclk) modes. sdata input the serial interface strobes data (sdata) in on the rising edge of sclk, msb first. the max5556 supports four different data formats, as detailed in figure 4. serial clock (sclk) sclk strobes the individual data bits at sdata into the dac. the max5556 operates in one of two modes: internal serial clock mode or external serial clock mode. external sclk mode the max5556 operates in external serial clock mode when sclk activity is detected. the device returns to internal serial clock mode if no sclk signal is detected for one lrclk period. figure 5 details the external serial clock mode timing parameters. figure 5. external sclk serial timing diagram figure 4. max5556 data format timing t slrh t slrs t sdh sdata sclk lrclk t sds t sclkl t sclkh t sclk msb msb lsb lsb -2 -3 -4 -5 +5 +4 +3 +2 +1 -1 -2 -3 -4 +5 +4 +3 +2 +1 lrclk sclk sdata data directed to outl -1 internal serial clock mode external serial clock mode ? i 2 s, 16-bit data and internal sclk = 32 x f s if mclk/ lrclk = 256 or 512 ? i 2 s, up to 24 bits of data and internal sclk = 48 x f s if mclk/ lrclk = 384 ? i 2 s, up to 24 bits of data ? data valid on rising edge of sclk data directed to outr www.maximintegrated.com maxim integrated 9 max5556 low-cost stereo audio dac downloaded from: http:///
internal sclk mode the max5556 transitions from external serial clock mode to internal serial clock mode if no sclk signal is detected for one lrclk period. in internal clock mode, sclk is derived from and is synchronous with mclk and lrclk (operation in internal clock mode is identical to an external clock mode when lrclk is synchronized with mclk). figure 6 details the internal serial clock mode timing parameters. figure 7 details the generation of the internal clock. figure 7. internal serial clock generation figure 6. internal sclk serial timing diagram internal sclk mclk lrclk sdata 1 n/2* n* *n = mclk/sclk. sdata internal sclk lrclk t isclkr t isds t isdh t isclk www.maximintegrated.com maxim integrated 10 max5556 low-cost stereo audio dac downloaded from: http:///
left/right clock input (lrclk) lrclk is the left/right clock input signal for the 3-wire interface and sets the sample frequency (f s ). on the max5556, drive lrclk low to direct data to outl or lrclk high to direct data to outr (figure 4). the max5556 accepts data at lrclk audio sample rates from 2khz to 50khz. master clock (mclk) mclk accepts the master clock signal from an external clocking device and is used to derive internal clock fre - quencies. set the mclk/lrclk ratio to 256, 384, or 512 to achieve the internal serial clock frequencies listed in table 1. table 2 details the mclk/lrclk ratios for three sample audio rates. the max5556 detects the mclk/lrclk ratio during the initialization sequence by counting the number of mclk transitions during a single lrclk period. mclk, sclk, and lrclk must be synchronous signals. data formatsmax5556 i 2 s left-justiied data format the max5556 accepts data with an i 2 s left-justified data format, accepting 16 or 24 bits of data. sdata accepts data in twos complement format with the msb first. the msb is valid on the second sclk rising edge after lrclk transitions low to high or high to low (figure 4). drive lrclk low to direct data to outl. drive lrclk high to direct data to outr. the number of sclk pulses with lrclk high or low determines the number of bits transferred per sample. if fewer than 24 bits of data are written, the remaining lsbs are set to 0. if more than 24 bits are written, any bits after the lsb are ignored. the max5556 accepts up to 24 bits of data in external serial clock mode or when the mclk/lrclk ratio is 384 (internal serial clock = 48 x f s ) in internal serial clock mode. the dac also accepts 16 bits of data in internal serial clock mode when the mclk/lrclk ratio is 256 or 512 (internal serial clock = 32 x f s ). external analog filter use an external lowpass analog filter to further reduce harmonic images, noise, and spurs. the external analog filter can be either active or passive depending upon per - formance and design requirements. for example filters, see figures 8 and 9 and the applications information section. careful attention should be paid when selecting capacitors for audio signal path applications. npo and c0g types are recommended as are aluminum electro - lytics and low-esr tantalum varieties. use of generic ceramic types is not recommended and may result in degraded thd performance. always consult manufactur - ers data sheets and applications information. figure 8. passive component analog output filter table 2. mclk/lrclk ratios table 1. internal and external clock frequencies lrclk (khz) mclk (mhz) mclk/lrclk = 256 mclk/lrclk = 384 mclk/lrclk = 512 32 8.1920 12.2880 16.3840 44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760 internal serial clock frequency external serial clock frequency mclk/lrclk = 256 or 512 mclk/lrclk = 384 32 x f s 48 x f s user deined (figure 4) max5556 outr outl 100k ? 100k ? r = 560 ? r = 560 ? c = 1.5nf c = 1.5nf www.maximintegrated.com maxim integrated 11 max5556 low-cost stereo audio dac downloaded from: http:///
figure 9. active component analog output filter outr 33pf outl +5v 33pf +5v 56pf 56pf 24.3k ? 5.23k ? 10k ? 59k ? 10k ? 59k ? 5.23k ? 24.3k ? v bias 2.4v v bias 2.4v max5556 www.maximintegrated.com maxim integrated 12 max5556 low-cost stereo audio dac downloaded from: http:///
pop and click suppression the max5556 features a pop and click supression rou - tine to reduce the unwanted audible effects of system transients. this routine produces glitch-free operation at the outputs during power-on, loss of clock, or invalid clock conditions. see figure 10 for a detailed state dia - gram during transient conditions. figure 10. internal state diagram no power applied outputs held at ground outputs linearly ramped to dc quiescent levels (< 1 second) internal registers initialized (mute) soft-start volume ramping outputs immediately returned to dc quiescent levels invalid ratio detected mclk time out sclk int/ext mode changed lrclk loss outputs held at current levels valid clock ratio re-established valid clock ratio re-established valid clock ratio established power-up loss- of- power event normal operation (full volume) lofclofc lofc lofc = loss-of-clock event lofc outputs immediately returned to ground www.maximintegrated.com maxim integrated 13 max5556 low-cost stereo audio dac downloaded from: http:///
power-up once the max5556 recognizes a valid mclk/lrclk ratio (256, 384, or 512), the analog outputs (outr and outl) are enabled in stages using a glitchless ramping routine. first, the outputs ramp up to the quiescent output voltage at a rate of 5v/s typ (see figure 11). after the outputs reach the quiescent voltage, the converted data stream begins soft-start ramping, achieving the full-scale operation over a 20ms period. if invalid clock signals are detected while the outputs are dc ramping to their quiescent state, the outputs stop ramping and hold their preset values until valid clock sig - nals are restored (figure 12). figure 12. invalid clock output response figure 11. power-up sequence time output voltage (outr or outl) invalid clock condition mute: v out_ immediately forced to dc quiescent level (2.4v) valid mclk/lrclk re-established and mclk equal or greater than minimum operating frequency v out_ soft-start ramping (20ms typ) time output voltage (outr or outl) v out_ ramps up to quiescent voltage at 5v/s (typ) v out_ begins to follow the data. the amplitude is ramped to full scale (20ms typ) valid mclk/lrclk ratio detected v out_ settles at quiescent voltage (2.4v) www.maximintegrated.com maxim integrated 14 max5556 low-cost stereo audio dac downloaded from: http:///
loss of clock and invalid clock conditions the max5556 mutes both outputs after detecting one of four invalid clock conditions. the device mutes its output to prevent propagation of pops, clicks, or cor - rupted data through the signal path. the max5556 forces the outputs to the quiescent dc voltage (2.4v) to prevent clicks in capacitive-coupled systems. invalid clock conditions include: 1) mclk/lrclk ratio changes between 256, 384, and 512 2) transition between internal and external serial- clock mode 3) invalid mclk/lrclk ratio 4) mclk falls below the minimum operating frequency 2khz when the mclk/lrclk ratio returns to 256, 384, or 512 and mclk is equal or greater than its minimum operating frequency, the max5556 output returns to its full-scale setting over a soft-start mute time of 20ms (figure 12). power-down when the positive supply is removed from the max5556, the output discharges to ground. when power is restored, the power-up ramp routine engages once a valid clock ratio is established (see the power-up section). avoid violating absolute maximum conditions by supply - ing digital inputs to the part or forcing voltages on the analog outputs during a loss-of-power event. applications information low-cost line-level solution connect the max5556 output through a passive output filter as detailed in figure 8 for a low-cost solution. this lowpass filter yields single-pole (20db/decade) roll-off at a corner frequency (f c ) determined by: c 1 f 2 rc = in the case of figure 8, f c is approximately 190khz. high-performance line-level solution for enhanced performance, connect the max5556 output to an active filter by using an operational amplifier as shown in figure 9. the use of an active filter allows for steeper roll-off, more efficient filtering, and also adds the capability of a programmable output gain. power-supply sequencing for correct power-up sequencing, apply v dd and then connect the input digital signals. do not apply digital sig - nals before v dd is applied. do not violate any of the absolute maximum ratings by removing power with the digital inputs still connected. to correctly power down the device, first disconnect the digital input signals, and then remove v dd . power-supply connections and ground management proper layout and grounding are essential for optimum performance. use large traces for the power-supply inputs and analog outputs to minimize losses due to para - sitic trace resistance. large traces also aid in moving heat away from the package. proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any switching noise from coupling into the audio signal. route the analog paths (gnd, v dd , outl, and outr) away from the digital signals. connect a 0.1f capacitor in parallel with a 4.7f capacitor as close to v dd as possible. low esr-type capacitors are recom - mended for supply decoupling applications. a small value c0g-type bypass capacitor located as close to the device as possible is recommended in parallel with larger values. www.maximintegrated.com maxim integrated 15 max5556 low-cost stereo audio dac downloaded from: http:///
package type package code outline no. land pattern no. 8 so s8+5 21-0041 90-0096 www.maximintegrated.com maxim integrated 16 max5556 low-cost stereo audio dac package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos downloaded from: http:///
revision number revision date description pages changed 0 5/06 initial release 1 2/11 added lead-free and automotive information, updated the absolute maximum ratings , removed all references to unreleased products max5557/max5558/max5559, updated the typical operating circuit 1C4, 7C19 2 8/13 updated ordering information 1 3 4/15 removed automotive reference from data sheet 1 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. ? 2015 maxim integrated products, inc. 17 max5556 low-cost stereo audio dac revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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